Today's semiconductor device manufacturing process has pushed resolution limits of certain tools and materials used in optical lithography to a point where catastrophic failures may occur for some configurations if not being designed carefully. In order to ensure that failing configurations do not occur in actual designs, manufacturers of semiconductor devices have typically relied upon some predefined design rules that device designers must follow. However, as geometries of device patterns continue to shrink, these design rules have often been found incapable of adequately safeguarding device patterns against all failure mechanisms.
In order to protect against design failure, attempts to modify currently existing design rules have led to design rules that are overly conservative and not competitive. In the meantime, the creation of a new set of design rules that is sufficiently detailed and comprehensive to ensure manufacturability of all designs, yet being succinct and compact such that device designers may learn quickly and adhere to it, is becoming increasingly difficult. For example, the need to satisfy requirements simultaneously of both process manufacturability and product design-ability has led to a proliferation of design rules, where new rules are introduced to clarify specific geometries. However, this trend cannot continue as the amount of time required to create and introduce new design rules and the amount of knowledge required by individual designers is growing at a rate that clearly cannot be sustained.
So far, various resolution enhancement techniques (RET), such as model based optical proximity correction (MBOPC) technique, have been developed to create photo-mask shapes that are capable of capturing design intent and avoiding catastrophic errors in the process of transferring device patterns to semiconductor wafers. The process or processing step of creating such photo-mask shapes is commonly known as a mask data preparation (MDP) process or processing step. Ideally, existing design rules shall ensure that the MDP process successfully print patterns without causing catastrophic errors. However, due to the need for competitive design rules, which as a result may have pushed process margins to their extremes, the MDP process may fall short at times. Moreover, tight process margins may create patterns that are sensitive to details of the MDP process. For example, failures may occur due to mask making constraints that inhibit some best mask artifacts and cause software limitations, and may occur due to locally inserted perturbation that was intended to correct a known problem, but adversely cause similar but not identical geometrical shapes to fail. The reality may be made even more difficult by the process variations that affect preponderantly some small areas of design. Here, it shall be noted that solutions specifically crafted for these cases are often, unfortunately, less than optimum for creating a robust mask and therefore the approach of crafting solutions is generally not considered as practical.
In order to improve manufacturability of these special case geometries, attempts have been made to create model-based design-for-manufacturability (DFM) tools. These tools apply the MDP step to process input layout data first, and use the processed layout data to simulate the patterning process, typically including impact which may be caused by process variations, and create a set of contours or contour curves. The contours represent expected locations of patterns when being printed on a wafer. The contours may subsequently be used for checking regions that violate manufacturability requirements in a manner analogous to the method, known as design-rule-checking (DRC), used for checking designs for design rule violations. DFM tools are typically employed by designers to improve manufacturability of their designs by finding and highlighting areas with poor manufacturability (“hot spots”). Once hot spots are located or identified, designers may make design modifications to improve manufacturability of the layout. Usually a DFM tool uses a predefined MDP algorithm consistently across the entire layout of interest. However, neither the DFM tool nor the designers have any knowledge of how each hot spot will be impacted by subsequent changes to the used MDP algorithm. In many cases, even though local changes to the MDP algorithm may help and result in adequate manufacturability, these changes fall within the realm of the wafer manufacturer, and not the design community.
FIG. 1 is a simplified flowchart illustration that shows a process of fixing design layout to improve printability of design patterns as is known in the art. More specifically, currently existing art tries to improve the manufacturability of design patterns by identifying hot spots through the use of a model-based DFM tool and performing manual design modifications to fix the hot spots. For example, a designer may first create a design layout (101) that represents geometries of patterns that are intended for printing on a wafer. This design layout is then divided into individual design layers (102), and processed by an OPC simulation algorithm (103) to obtain a set of photo-mask shapes (104). Here, it is understood that the step of OPC simulation algorithm (103) may include multiple steps or sub-steps of shape manipulation, which may be optionally automated, that may be carried out for various reasons including for example improving manufacturability of the device patterns. Computationally intensive optimization of source and/or mask shapes may also occur in this step, known as source-mask-optimization (SMO). Nevertheless, these shape manipulation steps and/or sub-steps are collectively referred to hereinafter as part of OPC simulation step (103) for the simplicity of description.
As is known in the art, mask shapes obtained at step 104, together with other process conditions (e.g., dose, focus, etc.), are used in a patterning simulation tool or system to simulate device patterns that may be transferred to a wafer (105). The simulation tool or system may generate a set of contours or contour curves (106) that represent the likelihood of the patterns. The contour curves are then checked at step (107) for possible violation of design rules such as space, width, enclosure, and the like. Areas or regions that are likely to cause catastrophic failures are marked (108). If there are regions or areas (109) that are candidates for causing failures, then the details of potential failures are communicated back to the designer for performing manual repair of the design layout (110). The above process is repeated until all the “hot spots” are repaired and no additional errors are found (109). Then, the final design or design layout (111) is released to the manufacturer.
It shall be noted that even though above design process, as being illustrated in FIG. 1, may contain information of mask shapes that the designer intends to print on a wafer, information such as, e.g., conditions of the MDP process used in the DFM tool may not be properly recorded and may have been lost during the process.
Creating designs that are process variation tolerant and maintaining competitive design density and electrical performance require designers applying design rules that are not extra conservative for failure avoidance. It is generally not a trivial task to strike a right balance or tradeoff between identifying a potentially failing design geometry and having a designer fix the geometry with a model-based DFM tool, and applying a post tape-out design fix approach. Attaining a proper tradeoff between the two in the shortest possible development cycle remains a major challenge in the industry.